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Agilent HDMP-2634 2.5/1.25 GBd Serdes Circuit
Data Sheet
Description This data sheet describes the HDMP-2634 Serdes device for 2.5 GBd serial data rates. The HDMP-2634 Serdes is a silicon bipolar integrated circuit in a metallized QFP package. It provides a low-cost physical layer solution for 2.5 GBd serial link interfaces including a complete Serialize/Deserialize (Serdes) function with transmit and receive sections in a single device. The HDMP-2634 is also capable of operating on 1.25 GBd serial links. Input pins TX_RATE and RX_RATE select the data rates on the transmit and receive sides, respectively. As shown in Figure 1, the transmitter section accepts 10-bit wide parallel SSTL_2 data (TX[0:9]) and a 125 MHz SSTL_2 byte clock (TBC) and serializes them into a highspeed serial stream. The parallel data is expected to be "8B/10B" encoded data or equivalent. At the source, TX[0:9] and TBC switch synchronously with respect to a 125 MHz clock internal to the sender. New data are emitted on both edges of TBC; this is called Double Data Rate (DDR). The HDMP-2634 finds
a sampling window between the two edges of TBC to latch TX[0:9] data into the input register of the transmitter section when TX_RATE=1. If TX_RATE=0, the user must ensure no data transitions on the falling edge of TBC and this edge is used to latch in parallel data resulting in a 1.25 GBd serial stream. The transmitter section's PLL locks to the 125 MHz TBC. This clock is then multiplied by 20 to generate the 2500 MHz serial clock for the high-speed serial outputs. The high-speed outputs are capable of interfacing directly to copper cables or PCB traces for electrical transmission or to a separate fiber optic module for optical transmission. The high-speed outputs include usercontrollable skin-loss equalization to improve performance when driving copper lines. The receiver section accepts a serial electrical data stream at 1.25 or 2.5 GBd and recovers 10-bit wide parallel data. The receiver PLL locks onto the incoming serial signal and recovers the
Features * 10-bit wide parallel Tx, Rx busses * 125 MHz TBC and RBC[0:1] * Option to set Tx and Rx serial data rates separately * Parallel data I/O, clocks and control compatible with SSTL_2 * Differential PECL or LVTTL REFCLK at 125 MHz * Double data rate transfers * Source synchronous clocking of transmit data * Source centered or source synchronous clocking of receive data * Dual or single receive byte clocks * Parallel loopback mode * Differential BLL serial I/O with on-chip source termination * 14 mm, 64-pin MQFP package * Single +3.3 V power supply Applications * Gigabit ethernet channel aggregation trunks * Fast serial backplanes * Clusters Ordering Information Part Number Parallel I/O HDMP-2634 SSTL_2
high-speed incoming clock and data. The serial data is converted back into 10-bit parallel data, optionally recognizing the first seven bits of the K28.5+ comma character to establish byte alignment. If K28.5+ detection is enabled, the receiver section is able to detect comma characters at 1.25 GBd or 2.5 GBd depending on the value of the RX_RATE pin. The recovered parallel data is presented at SSTL_2 compatible outputs RX[0:9], along with a pair of 125 MHz SSTL_2 clocks, RBC[0] and RBC[1], that are 180 degrees out of phase from one another and which represent the remote clock. Rising edges of RBC[0] and RBC[1] may be used to latch RX[0:9] data at the destination. Alternatively, both edges of either RBC[1] or RBC[0] may be used to latch Rx data (DDR). The preceding applies when RX_RATE=1 and RBC_SYNC=0. For short distances, there may be a need to have ASICs communicate directly using parallel Tx and Rx lines without the serdes intermediary. To enable this, the Tx and Rx parallel timing schemes must be symmetrical. When RBC_SYNC=1 and RX_RATE=1 such symmetry is obtained. In this mode, the RX[0:9] lines switch simultaneously with the rising and falling edges of RBC[1] or RBC[0] just as the TX[0:9] lines switch simultaneously with TBC. If RX_RATE=0 and RBC_SYNC=1 then the RX[0:9] lines switch with the rising edges of RBC[1] just as the TX[0:9] lines switch with the rising edges of TBC. If RBC_SYNC=0 then RX[0:9] data may be latched on the rising edges of RBC[1] and RBC[0]. In this latter mode, the RBC[0:1] clocks operate at a 62.5 MHz rate.
In summary, by setting RBC_SYNC=0 the timing of transmit and receive parallel data with respect to TBC and RBC[0:1] may be arranged so that the upstream protocol device can generate and latch data very simply. This is the source centered mode of operation (case A and C in Table 1, page 8). Alternatively, setting RBC_SYNC=1 provides for timing symmetry between Tx and Rx parallel lines at both 1.25 GBd and 2.5 GBd rates. This is the source synchronous mode of opertion (case B and D in Table 1, page 8). Note when EN_CDET=1, the first transition of byte 0 of a comma will either coincide with the rising edge of RBC[1] or precede it. This applies regardless of the RX_RATE setting. Table 1 summarizes the behavior of the Rx parallel section under all values of RX_RATE and RBC_SYNC. For test purposes, the transceiver provides for on-chip parallel to parallel local loopback functionality controlled through the EWRAP pin. Additionally, the byte alignment feature via detection of the first seven bits of the K28.5+ character may be disabled. This may be useful in proprietary applications which use alternative methods to align the parallel data. The HDMP-2634 accepts either a differential PECL or a LVTTL reference clock input at 125 MHz. HDMP-2634 Block Diagram The HDMP-2634 (Figure 2) is designed to transmit and receive 10-bit wide parallel data over high-speed serial communication lines. The parallel data applied to the transmitter is expected to be encoded per the 8B/10B encoding scheme with special reserved
characters for link management purposes. Other encoding schemes will also work as long as they provide DC balance and a sufficient number of transitions. The HDMP-2634 incorporates the following: * SSTL_2 Parallel I/O * High Speed Phase Locked Loops * Parallel to Serial Converter * High Speed Serial Clock and Data Recovery Circuitry * Comma Character Recognition per Fibre Channel Specifications * Byte Alignment Circuitry * Serial to Parallel Converter
INPUT LATCH
The transmitter accepts 10-bit wide single ended SSTL_2 parallel data at inputs TX[0:9]. The SSTL_2 TBC clock provided by the sender of the transmit data is used as the transmit byte clock. The TX[0:9] and TBC signals must be properly aligned as shown in Figure 3. If TX_RATE=1, TX[0:9] data are latched between both edges of TBC. If TX_RATE=0, TX[0:9] data are latched on the falling edge of TBC. The TX[0:9] and TBC inputs are unterminated SSTL_2 inputs per section 4.1 of the SSTL_2 standard (Figure 11).
TX PLL/CLOCK GENERATOR
The Transmitter Phase Locked Loop and Clock Generator block is responsible for generating all internal clocks needed by the transmitter section to perform its functions. These clocks are based on the supplied transmit byte clock (TBC). Incoming data must be synchronous with TBC (Figures 3a-3b). Use of TBC to determine sampling points to latch data obviates the need for PLLs in the data source.
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HDMP-2634 TX_RATE TBC TX[0:9] PLL ASIC EWRAP RBC[0:1] RX[0:9] COM_DET RX_RATE REF_RATE RBC_SYNC PLL SI TRANSMITTER SECTION
SO
RECEIVER SECTION
REFCLK[0:1]
EN_CDET
Figure 1. Typical application using HDMP-2634.
INPUT LATCH
TX[0:9]
FRAME MUX
OUTPUT SELECT
SO
EWRAP TBC TXCAP0 TXCAP1 RXCAP0 RXCAP1 REFCLK[0:1] RX PLL CLOCK RECOVERY REF_RATE RBC_SYNC TX PLL CLOCK GENERATOR
TX CLOCKS
INPUT SELECT
SI
TX_RATE RX_RATE RBC[0:1]
RX CLOCKS
OUTPUT DRIVER
RX[0:9]
FRAME DEMUX AND BYTE SYNC
INPUT SAMPLER
COM_DET
EN_CDET
Figure 2. Block diagram of HDMP-2634.
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FRAME MUX
RX PLL/CLOCK RECOVERY
The FRAME MUX accepts 10-bit wide parallel data from the INPUT LATCH. Using internally generated high-speed clocks, this parallel data is multiplexed into a 2.5 GBd serial data stream. The data bits are transmitted sequentially from TX[0] to TX[9]. The leftmost bit of K28.5+ is on TX[0].
OUTPUT SELECT
The OUTPUT SELECT block picks the serial data to drive on to the serial output line. In normal operation, the serialized TX[0:9] data is placed at SO . In parallel loopback (EWRAP=1) mode, the SO pins are held static at logic 1 and the internal serial output signal going to the INPUT SELECT block of the receiver section is used to generate RX[0:9]. In addition, the OUTPUT SELECT block allows the user to control the amount of pre-emphasis used on the SO pins. If pre-emphasis is used, 01 and 10 transitions on SO have greater amplitude than 00 and 11 transitions. This increased amplitude is used to offset the effects of skin loss and dispersion on long PCB transmission lines. Pre-emphasis is controlled by the EQAMP pin (Table 2 and Figure 9).
INPUT SELECT
The Receiver Phase Locked Loop and Clock Recovery block is responsible for frequency and phase locking onto the incoming serial data stream and recovering the bit and byte clocks. An automatic locking feature allows the Rx PLL to lock onto the input data stream without external PLL training controls. It does this by continually frequency locking onto the 125 MHz reference clock, and then phase locking onto the selected input data stream. An internal signal detection circuit monitors the presence of the input and invokes the phase detection as the data stream appears. Once bit locked, the receiver generates the highspeed sampling clock for the input sampler.
INPUT SAMPLER
block to select the proper parallel data edge out of the bit stream so that the next comma character starts at RX[0]. When a comma character is detected and realignment of the receive byte clock RBC[0:1] is necessary, these clocks are stretched (never slivered) to the next correct alignment position. RBC[0:1] will be aligned by the start of the next ordered set (two-byte group) after K28.5+ is detected. The start of the next ordered set will be aligned with the rising edge of RBC[1], independent of the RX_RATE pin setting. Per the Fibre Channel encoding scheme, comma characters must not be transmitted in consecutive bytes so that the receive byte clocks may maintain their proper recovered frequencies.
OUTPUT DRIVERS
The INPUT SAMPLER is responsible for converting the serial input signal into a retimed bit stream. To accomplish this, it uses the high-speed serial clock generated from the RX PLL/ CLOCK RECOVERY block. This serial bit stream is sent to the FRAME DEMUX AND BYTE SYNC block.
FRAME DEMUX AND BYTE SYNC
The OUTPUT DRIVERS present the 10-bit parallel recovered data (RX[0:9]) properly aligned to the receive byte clock (RBC[0:1]) as shown in Figures 5a-5d and Table 1. These output drivers provide single ended SSTL_2 compatible signals.
RECEIVER LOSS OF SIGNAL
The INPUT SELECT block picks the serial data that will be parallelized to drive RX[0:9]. In normal operation, serial data is accepted at SI . In parallel loopback (EWRAP=1) mode, the internal serial output signal from the OUTPUT SELECT block of the transmitter section is used to generate RX[0:9].
The FRAME DEMUX AND BYTE SYNC block is responsible for restoring the 10-bit parallel data from the high-speed serial bit stream. This block is also responsible for recognizing the first seven bits of the K28.5+ positive disparity comma character (0011111xxx). When recognized, the FRAME DEMUX AND BYTE SYNC block works with the RX PLL/CLOCK RECOVERY
The RECEIVER LOSS OF SIGNAL block examines the peak-to-peak differential amplitude at the SI input. When this amplitude is too small, RX_LOS is set to 1, and RX[0:9] are set to logic one (1111111111). This prevents generation of random data at the RX[0:9] pins when the serial input lines are disconnected. When the signal at SI is a valid amplitude, RX_LOS is set to logic 0, and the output of the INPUT SELECT block is passed through.
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SSTL_2 COMPATIBILITY
The HDMP-2634 works with protocol (FC-1 or MAC) devices whose VDDQ voltage is nominally 2.5 V. Note that the HDMP-2634 works with a single VCC supply of 3.3 V. Nonetheless, RX[0:9] and RBC[0:1] generate output voltages that are compatible with section 4.1 of the SSTL_2 standard and are not meant to be terminated in 50 . In addition, the HDMP-2634 provides a VREFR output pin which may be used at the protocol IC in order to differentially detect a high or a low on RX[0:9]. Alternatively, this voltage may be generated on the PCB using a resistor divider from VDDQ or V CC while ignoring the VREFR output of the HDMP2634. The HDMP-2634 expects SSTL_2 compatible signals at the TX[0:9] and TBC pins. These pins are unterminated per section 4.1 of the SSTL_2 standard (Figure 11). The VREFT input pin is used by the HDMP-2634 to differentially detect a high or low on TBC and TX[0:9]. VREFT may be generated by the protocol device or on the PCB using a resistor divider from VDDQ or VCC.
MULTI-RATE OPERATION
node that is capable of operating at 1.25 GBd and 2.5 GBd rates is establishing a link with a node that is capable of only 2.5 GBd. Both nodes will start emitting at 2.5 GBd because this is their highest rate. The first node will try receiving at 1.25 GBd rate. It will not succeed and will therefore try 2.5 GBd reception, which will succeed. The second node is set to 2.5 GBd and has been receiving correct data. These two nodes will settle to 2.5 GBd. If the second node in the example above operated at 1.25 GBd only, then the first node would see intelligible 1.25 GBd data and set its TX_RATE=0, at which time the second node would also start seeing intelligible data. These nodes would settle to 1.25 GBd. If both nodes are 1.25/2.5 GBd capable, then they will settle to 2.5 GBd. With this algorithm, nodes need not have a common lowest common denominator data rate to interoperate.
The HDMP-2630/2631 provide hooks for initializing multi-rate links. A possible algorithm operates as follows. In a point to point link, each node sets its TX_RATE input pin high to transmit at the highest possible data rate. At the same time, each node tries different values of RX_RATE to see at which data rate intelligible data is received. Once this data rate is found, TX_RATE is set to enable this rate. For example, suppose a
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HDMP-2634 Transmitter Section Timing Characteristics TA = 0C to TC = 85C, VCC = 3.15 V to 3.45 V Symbol tTXCT tTXCV tTXSETUP tTXHOLD t_txlat [1] Parameter TX[0:9] Input Data and TBC Clock Valid Time (TX_RATE = 1) TX[0:9] Setup Time to Falling Edge of TBC (TX_RATE = 0) TX[0:9] Hold Time from Falling Edge of TBC (TX_RATE = 0) Transmitter Latency Units ps ps ps Min. 2400 1400 1400 0.8 ns + 8.5 bits Typ. Max. 1600 TX[0:9] Input Data and TBC Clock Transition Range (TX_RATE = 1) ps
Note: 1. The transmitter latency, as shown in Figure 4, is defined as the time between the leading edge of a parallel data word and the leading edge of the first transmitted serial output bit of that data word.
TXCT
TX[0:9]
TXCV
TXCV
TBC
8.00 ns
Figure 3a. Parallel transmitter section timing. TX_RATE = 1.
TX[0:9]
TXSETUP
TXHOLD
TBC
8.00 ns
Figure 3b. Parallel transmitter section timing. TX_RATE = 0.
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10-BIT CHAR A
10-BIT CHAR B
SO TX[0] TXLAT
TX[0..9]
10-BIT CHAR B
10-BIT CHAR C
TBC
Figure 4. Transmitter latency. TX[0] is first bit on SO.
HDMP-2634 Receiver Section Timing Characteristics TA = 0C to T C = 85C, VCC = 3.15 V to 3.45 V Symbol f_lock b_sync [1,2] t_rxlat[3] Parameter Frequency Lock at Powerup with REFCLK Active Bit Sync Time Receiver Latency Units s bits 200 13.5 bits +2.5 ns Min. Typ. Max. 500 2500
Notes: 1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3. 2. Tested using C PLL = 0.1 F. 3. The receiver latency, as shown in Figure 6, is defined as the time between the leading edge of the first received serial bit of a parallel data word and the leading edge of the corresponding parallel output word.
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Table 1. HDMP-2634 RX, RBC[0:1] Timing Dependence on RX_RATE and RBC_SYNC. Input Settings Case RX_RATE RBC_SYNC A 0 0 Resulting Behaviors SI Rate (GBd) RBC Rate (MHz) Timing Diagrams for RBC0, RBC1, RX[0:9] 1.25 62.5
RBC0 RBC1 RX[0:9]
B
0
1
1.25
125
RBC0 RBC1 RX[0:9]
C
1
0
2.5
125
RBC0 RBC1 RX[0:9]
D
1
1
2.5
125
RBC0 RBC1 RX[0:9]
Z0 = 50 SSTL_2 OUTPUT DRIVER DELAY = 0.5 - 2.0 ns
MEASUREMENT POINT CLOAD = 4-20 pF -100 A <= ILOAD <= 100 A
Figure 5. Test conditions for SSTL_2 output driver.
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16.00 ns
RBC0
RBC1
RXS RXH
RXS RXH
RX[0:9]
TA-B
Figure 5a. Receiver section timing - case A.
Case A of Table 1. (RX_RATE = 0, RBC_SYNC = 0) TA = 0C to T C = 85C, VCC = 3.15 V to 3.45 V Symbol tRXS tRXH tA-B tDUTY Parameter RX[0:9] Setup Time to RBC1 or RBC0 (Data Valid Before) RX[0:9] Hold Time from RBC1 or RBC0 (Data Valid After) RBC1 Rising Edge to RBC0 Rising Edge Skew RBC[0:1] Duty Cycle Units ps ps ns % Min. 2700 1500 7.5 40 8.5 60 Typ. Max.
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8.00 ns
RBC0
RBC1
RXS RXH
RX[0:9]
Figure 5b. Receiver section timing - case B.
Case B of Table 1. (RX_RATE = 0, RBC_SYNC = 1) TA = 0C to TC = 85C, VCC = 3.15 V to 3.45 V Symbol tRXS tRXH Parameter RX[0:9] Setup Time to RBC1 or RBC0 (Data Valid Before) RX[0:9] Hold Time from RBC1 or RBC0 (Data Valid After) Units ps ps Min. 1500 1700 Typ. Max.
8.00 ns
RBC0
RBC1
RXS RXH
RX[0:9]
RXS RXH
TA-B
Figure 5c. Receiver section timing - case C.
Case C of Table 1. (RX_RATE = 1, RBC_SYNC = 0) TA = 0C to TC = 85C, VCC = 3.15 V to 3.45 V Symbol tRXS tRXH tA-B tDUTY Parameter RX[0:9] Setup Time to RBC1/0 (Data Valid Before) RX[0:9] Hold Time from RBC1/0 (Data Valid After) RBC1 Rising Edge to RBC0 Rising Edge Skew RBC[0:1] Duty Cycle Units ps ps ns % Min. 800 1000 3.8 40 4.2 60 Typ. Max.
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8.00 ns
RBC0
RBC1
RXCV
RXCT
RX[0:9]
Figure 5d. Receiver section timing - case D.
Case D of Table 1. (RX_RATE = 1, RBC_SYNC = 1) TA = 0C to T C = 85C, VCC = 3.15 V to 3.45 V Symbol tRXCT tRXCV Parameter RX[0:9] Output Data and RBC Clock Transition Range RX[0:9] Output Data and RBC Clock Valid Time Units ps ps 2500 Min. Typ. Max. 1500
10-BIT CHAR B
10-BIT CHAR C
SI RX[0] RXLAT RX[9]
RX[0:9]
10-BIT CHAR A
10-BIT CHAR B
RBC[0:1]
Figure 6. Receiver latency. First bit on SI drives RX[0].
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HDMP-2634 Absolute Maximum Ratings Sustained operation at or beyond any of these conditions may result in long-term reliability degradation or permanent damage, and is not recommended. Symbol VCC Tstg TC Tj VIN,PECL VIN,SSTL Parameter Supply Voltage Storage Temperature Case Temperature Junction Temperature LVPECL Input Voltage SSTL_2 Input Voltage Units V C C C V V Min. -0.5 -65 0 0 -0.5 -0.5 Max. 4.0 150 95 125 VCC + 0.5[1] VCC + 0.5[1]
Note: 1. Must remain less than or equal to absolute maximum VCC voltage of 4.0 V.
HDMP-2634 Guaranteed Operating Rates TA = 0C to TC = 85C, VCC = 3.15 V to 3.45 V Parallel Clock Rate (MHz) Min. Max. 124 126 Serial Baud Rate (GBd) Min. Max. 1.24 1.26 Serial Baud Rate (GBd) Min. Max. 2.48 2.52
HDMP-2634 Transceiver REFCLK and TBC Requirements TA = 0C to TC = 85C, VCC = 3.15 V to 3.45 V Symbol f Ftol Symm Parameter Nominal Frequency Frequency Tolerance Symmetry (Duty Cycle) Units MHz ppm % -100 40 Min. Typ. 125 100 60 Max.
HDMP-2634 DC Electrical Specifications TA = 0C to TC = 85C, VCC = 3.15 V to 3.45 V Symbol ICC, TRx[1] PD, TRx [1] Parameter Transceiver Supply Current (total of all supplies) Transceiver Total Power Dissipation Units mA mW Min. Typ. 620 2050 Max. 780 2700
Note: 1. Measurement Conditions: Tested sending 2.5 GBd 27-1 PRBS sequence from a serial BERT with SO outputs differentially terminated using a 100 resistor.
HDMP-2634 PECL DC Electrical Specifications for REFCLK[0:1] TA = 0C to TC = 85C, VCC = 3.15 V to 3.45 V Symbol VIH,PECL VIL,PECL Parameter PECL Input High Voltage Level PECL Input Low Voltage Level Units V V Min. 2.10 1.30 Typ. Max. 2.60 1.80
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HDMP-2634 LVTTL DC Electrical Specifications for REFCLK[1] TA = 0C to T C = 85C, VCC = 3.15 V to 3.45 V Symbol VIH,LVTTL VIL,LVTTL Parameter LVTTL Input High Voltage Level LVTTL Input Low Voltage Level Units V V Min. 2.00 0.80 Typ. Max.
SSTL_2 I/O Parameters HDMP-2634 Recommended DC Operating Conditions and DC Electrical Characteristics TA = 0C to T C = 85C, VCC = 3.15 V to 3.45 V, VDDQ = 2.30 V to 2.70 V. VDDQ is the FC-1/MAC device I/O supply voltage. SSTL_2 inputs can receive LVTTL signals successfully. SSTL_2 outputs do not output LVTTL compliant levels. Symbol VREFT VIH VIL VREFR VOH VOL Parameter SSTL_2 Input Reference Voltage Input High Voltage Input Low Voltage SSTL_2 Output Reference Voltage Output High Voltage Output Low Voltage Units V V V V V V Min. 1.15 VREFT +0.35 -0.30 1.15 VREFR +0.38 GND 1.25 Typ. 1.25 Max. 1.35 VDDQ +0.30 VREFT -0.35 1.35 VDDQ VREFR -0.38
HDMP-2634 AC Electrical Specifications TA = 0C to T C = 85C, VCC = 3.15 V to 3.45 V Symbol tr,REFCLK tf,REFCLK trd, HS_OUT tfd, HS_OUT tr,SSTL tf,SSTL VIP,HS_IN VOP,HS_OUT [1] VOP,HS_OUT [1] Parameter REFCLK[0:1] PECL Input Rise Time, VIL,PECL to VIH,PECL REFCLK[0:1] PECL Input Fall Time, VIH,PECL to VIL,PECL HS_OUT Differential Rise Time, 20% - 80% HS_OUT Differential Fall Time, 20% - 80% SSTL Input Rise Time, VIL,SSTL to VIH,SSTL SSTL Input Fall Time, VIH,SSTL to VIL,SSTL HS_IN Input Peak-To-Peak Differential Voltage HS_OUT Output Pk-Pk Diff. Voltage (Z0 = 50 , Fig. 9) HS_OUT Output Pk-Pk Diff. Voltage (Z0 = 75 , Fig. 9) Units ns ns ps ps ns ns mV mV mV 200 800 1100 1050 1400 160 160 1.5 1.5 2000 2000 2000 Min. Typ. Max. 1.5 1.5
Note: 1. Output Differential Voltage defined as (SO+ - SO-). Measurement made with Tx pre-emphasis off (EQAMP tied to VCC with a 100 resistor).
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HDMP-2634 Transmitter Section Output Jitter Characteristics TA = 0C to TC = 85C, VCC = 3.15 V to 3.45 V Symbol RJ[1] DJ[2] DJ Parameter Random Jitter at SO (1 deviation of the 50% crossing point) Deterministic Jitter at SO (peak-to-peak), K28.5+/K28.5- Pattern Deterministic Jitter at SO (peak-to-peak), CRPAT[3] Pattern Units ps ps ps Typ. 6.2 22 31
Notes: 1. Defined by Fibre Channel Specification X3.230-1994 FC-PH, Annex A, Section A.4.4 (oscilloscope method) and tested using the setup shown in Figure 8b. 2. Defined by Fibre Channel Specification X3.230-1994 FC-PH, Annex A, Section A.4.3 and tested using the setup shown in Figure 8a. 3. Defined in the Fibre Channel Technical Report "Methodologies for Jitter Specification," Annex B, and tested using the setup shown in Figure 8a.
Figure 7a. Serial output eye diagram with nominal Tx pre-emphasis.
Figure 7b. Serial output random jitter with Tx pre-emphasis off.
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DETERMINISTIC JITTER MEASUREMENT METHOD HP 83480A SCOPE SERIAL BERT HP 70004A DISPLAY HP 70842A ERROR DETECTOR
CLOCK IN DATA IN
TRIGGER FROM PGEN CLOCK OR TRIGGER
HP 70841A PATTERN GENERATOR
CLOCK OUT DATA TRIGGER OUT+ N/C
HP 70311A CLOCK SOURCE
CLOCK OUT
DATA OUT-
CLOCK IN
CLOCK OUT
MODULATION
2.5 GHz RBC1 TBC DIV 2 SI HDMP-2634 2.5 GBd SO SERDES REFCLK 125 MHz 10 bits DIVIDE BY 20
DIV 10
RANDOM JITTER MEASUREMENT METHOD HP 83480A SCOPE SERIAL BERT HP 70004A DISPLAY HP 70842A ERROR DETECTOR
CLOCK IN DATA IN
TRIGGER FROM PGEN CLOCK OR TRIGGER
HP 70841A PATTERN GENERATOR
CLOCK OUT DATA TRIGGER OUT+ N/C
HP 70311A CLOCK SOURCE
CLOCK OUT
DATA OUT-
CLOCK IN
CLOCK OUT
MODULATION
STATIC K28.7 0011111000 Tx[0:9]
2.5 GHz DIV 2 TBC DIV 10 REFCLK 125 MHz
HDMP-2634 2.5 GBd SERDES SO
DIVIDE BY 20
Figure 8a-b. Transmitter deterministic and random jitter measurement method.
HDMP-2634 Thermal Characteristics TA = 0C to T C = 85C, VCC = 3.15 V to 3.45 V Symbol jc[1] Parameter Thermal Resistance, Junction to Case Units C/W Typ. 9.3
Note: 1. Based on independent package testing by Agilent. ja for these devices is 38C/W for the HDMP-2634. ja is measured on a standard 3x3" FR4 PCB in a still air environment. To determine the actual junction temperature in a given application, use the following equation: Tj = Tc + (jc x PD), where Tc is the case temperature measured on the top center of the package and P D is the power being dissipated.
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HDMP-2634 Pin Input Capacitance Symbol CINPUT Parameter Input Capacitance on SSTL input pins Units pF Typ. 1.6
(SO+) - (SO-)
STEADY-STATE OUTPUT LEVEL MAXIMUM OUTPUT LEVEL STEADY-STATE OUTPUT LEVEL 1.11 V 820 mV 570 mV
MAXIMUM OUTPUT LEVEL 1.11 V 1.28 V 1.44 V
EQAMP SETTING 100 to VCC (NO PRE-EMPHASIS) FLOATING (NOMINAL PRE-EMPHASIS) SHORTED TO GND (MAXIMUM PRE-EMPHASIS)
ALL VALUES MEASURED IN A 50 ENVIRONMENT WITH VCC = 3.3 V AND TA = 25C.
1 BIT
Figure 9. Tx pre-emphasis control using EQAMP pin.
HS_OUT
VCC
HS_IN
VCC_TXHS Zo Zo VCC
VCC
+SO 0.01 F
Zo = 50
+SI
+ - -SO 0.01 F GND ESD
PROTECTION
Zo = 50 -SI GND ESD
PROTECTION
+ -
GND_TXHS
GND
NOTE: HS_IN INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT. Z0 = 75 MAY ALSO BE USED.
Figure 10. HS_OUT and HS_IN simplified circuit schematic for HDMP-2634.
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VCC (SERDES) = 3.3 V
VCC (SERDES) R1
VCC (MAC) = 2.5 V 2.5 V FOR SSTL_2 VCC VDDQ VREFT
VCC 0.1 F VREFR R2
RX[0:9]
RS = 50 UNTERMINATED
DATAIN
TX[0:9]
RS = 50 USE TERMINATION, IF NECESSARY, TO DELIVER PROPER VOLTAGE SWINGS AT TX[0:9] VCC (MAC) R1
DATAOUT
VREFT R2 HDMP-2634 0.1 F
VREFR
MAC
NOTE: VREFR ON EACH DEVICE MAY BE USED TO DRIVE VREFT ON THE OTHER DEVICE INSTEAD OF USING THE CONFIGURATION ABOVE. VREFR SHOULD BE BYPASSED WITH 0.1 F IN THIS CASE. IF USED, R1 + R2 SHOULD BE 500-1000 . 1% RESISTORS SHOULD BE USED FOR R1 AND R2. WHEN USING THE CONFIGURATION ABOVE, VREFT TO THE MAC DEVICE SHOULD BE SET TO 1.25 V NOMINAL. USING THIS VALUE CENTERS VREFR RELATIVE TO THE RX[0:9] OUTPUT SWINGS PROVIDED BY THE HDMP-2634.
Figure 11. I-SSTL2 and O-SSTL2 simplified circuit schematic.
I/O Type Definitions I/O Type I-SSTL2 O-SSTL2 HS_OUT HS_IN C S Definition Input SSTL_2. These inputs will receive LVTTL-compliant signals successfully. Output SSTL_2. These outputs will not produce LVTTL-compliant signals. High Speed Output, ECL Compatible High Speed Input External Circuit Node Power Supply or Ground
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Table 2. Pin Definitions for HDMP-2634 Name EQAMP Pin 56 Type C Signal Output Equalization Amplitude Control: Controls the relative amount of equalization on the high-speed serial data outputs. Equalization is disabled by connecting a 100 resistor from EQAMP to VCC. The amount of equalization can be increased by either increasing the value (above 100 ) of a resistor connected from EQAMP to VCC, or decreasing the value of a resistor connected from EQAMP to GND. Maximum equalization is obtained by connecting EQAMP directly to GND. See Figure 9. Loop Enable: When high, the high speed serial output data is internally connected directly to the receiver circuit, bypassing the high-speed input and output buffers. The external high-speed data outputs SO are set high and SI inputs are ignored. Comma Detect Enable: When high, enables detection of comma character. Comma Detect Indicator: When high, indicates that a comma character of positive disparity (0011111xxx) has been detected on the high speed serial input line. Transmit Rate Set: If set to low, the HDMP-2634 reads TX[0:9] data on the falling edge of TBC and serializes it. This corresponds to a 1.25 GBd serial stream. If set to high, the HDMP-2634 reads TX[0:9] data between both edges of TBC and serializes it. This corresponds to a 2.5 GBd serial stream. Receive Rate Set: If set to low, the HDMP-2634 samples the incoming serial stream at 1.25 GBd and drives it on the RX[0:9] lines with the rising edge of RBC1. If set to high, the HDMP-2634 samples the incoming serial stream at 2.5 GBd and drives it on the RX[0:9] lines with the rising edges of RBC1 and RBC0. (Table 1.) Receive Byte Clock Synchronization Control: When RBC_SYNC=1, RX[0:9] data has the same relation to RBC[0:1] as TX[0:9] data has to TBC. ASICs designed using this mode have the option of avoiding a SERDES driven serial link and communicating directly on parallel lines, for short distances. Loss of Signal at the Receiver Detect: Indicates a loss of signal on the high-speed differential inputs, SI, as in the case where the transmission cable becomes disconnected. If SI >= 200 mV peak-to-peak differential, RX_LOS = logic 0. If SI < 200 mV and SI > 75 mV, RX_LOS = undefined. If SI =< 75 mV, RX_LOS = logic 1, RX[0:9]=1111111111. Serial Data Outputs: High speed outputs. These lines are active when not in parallel loop mode (EWRAP=0). When EWRAP is high, these outputs are held static at logic 1. Serial Data Inputs: High speed inputs. Serial data is accepted from SI inputs when EWRAP is low. Transmit Clock: Both edges of this input are used to determine the sampling window for transmit parallel data. The transmitter section accepts this signal as the frequency reference clock. It is multiplied by 20 to generate the outgoing serial bit clock and other internal clocks. Receive Byte Clocks: The receiver section recovers two receive byte clocks. These two clocks are 180 degrees out of phase. See Table 1 for timing relationships. Reference Clock: A 125 MHz clock supplied by the host system. It serves as the reference clock for the receive portion of the transceiver. These pins may be driven by a differential PECL clock source or a single ended LVTTL clock source. In the LVTTL case, REFCLK[1] is to be driven and REFCLK[0] is to be bypassed to GND via a 0.1 F capacitor.
EWRAP
19
I-SSTL2
EN_CDET COM_DET TX_RATE
24 27 14
I-SSTL2 O-SSTL2 I-SSTL2
RX_RATE
55
I-SSTL2
RBC_SYNC 10
I-SSTL2
RX_LOS
26
O-SSTL2
SO+ SO- SI+ SI- TBC
62 61 52 53 01
HS_OUT HS_IN I-SSTL2
RBC[1] RBC[0] REFCLK[1]
30 31 22
O-SSTL2 I-PECL or I-LVTTL I-PECL
REFCLK[0]
23
18
Table 2. Pin Definitions for HDMP-2634, continued Name TX[0] TX[1] TX[2] TX[3] TX[4] TX[5] TX[6] TX[7] TX[8] TX[9] RX[0] RX[1] RX[2] RX[3] RX[4] RX[5] RX[6] RX[7] RX[8] RX[9] TXCAP0 TXCAP1 RXCAP0 RXCAP1 VCC Pin 02 03 04 06 07 08 09 11 12 13 45 44 43 41 40 39 38 36 35 34 17 16 48 49 20 28 57 59 54 18 50 60 63 05 47 37 42 21 25 58 15 51 Type I-SSTL2 Signal Data Inputs: One 10-bit, encoded character to the SO serial outputs. TX[0] is the first bit transmitted. TX[0] is the least significant bit.
O-SSTL2
Data Outputs: One 10-bit encoded character from one of the SI serial inputs. RX[0] is the first bit received. When RX_LOS =1, there is a loss of input signal at SI, and these outputs are held static at logic 1. Refer to RX_LOS pin definition for more details.
C C S
Loop Filter Capacitor: A loop filter capacitor for the internal transmit PLL must be connected across the TXCAP0 and TXCAP1 pins. (typical value is 0.1 F) Loop Filter Capacitor: A loop filter capacitor for the internal receive PLL must be connected across the RXCAP0 and RXCAP1 pins. (typical value is 0.1 F) Logic Power Supply: Normally 3.3 volts. Used for internal PECL logic.
VCC_TXA VCC_RXA VCC_TXHS VREFT VREFR VCC_SSTL GND
S S S S S S S
Analog Power Supply: Normally 3.3 volts. Used to provide a clean supply line for transmit PLL and high speed analog cells. Analog Power Supply: Normally 3.3 volts. Used to provide a clean supply line for receive PLL and high speed analog cells. High Speed Supply: Normally 3.3 volts. Used only for the high speed transmit cell (HS_OUT). Noise on this line should be minimized for best operation. Voltage Reference Input: Used with I-SSTL2 inputs to the HDMP-2634. (Figure 11.) Voltage Reference Output: Used with O-SSTL2 outputs from the HDMP-2634. (Figure 11.) SSTL I/O Supply Voltage for SSTL_2. Normally 3.3 V. All necessary voltages for SSTL_2 operation are internally generated. Logic Ground: Normally 0 volts. This ground is used for internal PECL logic.
GND_TXA GND_RXA
S S
Analog Ground: Normally 0 volts. Used to provide a clean ground plane for the PLL and high-speed analog cells. Analog Ground: Normally 0 volts. Used to provide a clean ground plane for the receiver PLL and high-speed analog cells.
19
Table 2. Pin Definitions for HDMP-2634, continued Name Pin Type S S Signal High Speed Ground: Normally 0 volts. Used for HS_IN cell. SSTL Ground: Normally 0 volts. Used for SSTL_2 I/O. GND_TXHS 64 GND_SSTL 32 33 46 N/C 29
No Connect. Any voltage between GND and VCC may be applied to this pin.
VCC
R1 0 (OPTIONAL) EQAMP 100 R2 0 (OPTIONAL)
VCC
VCC L2 CB9 0.1 F C4* 10 F 1 H CB8 0.1 F CB7 0.1 F
VCC + C2* 10 F
CB11 0.1 F
CB10 0.1 F
64
63 62
61 60 59
58
57 56
55 54 53
52 51 50 49
GND_TXHS
EQAMP
VCC_TXHS SO+ SO- VCC_TXHS
RX_RATE VCC
1 2 3 4 CB12 0.1 F 5 6 7 8 9 10 11 12 13 14 15 16
SI+ GND_RXA
VCC_RXA RXCAP1
GND VCC
VCC
SI-
CPLLR 0.1 F
TBC TX[0] TX[1] TX[2] VREFT TX[3] TX[4] TX[5]
RXCAP0 VREFR GND_SSTL RX[0] RX[1] RX[2]
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CB5 0.1 F VCC
TX[6] RBC_SYNC TX[7] TX[8] TX[9] TX_RATE GND_TXA TXCAP1
UI HDMP-2634
VCC_SSTL RX[3] RX[4] RX[5] RX[6] VCC_SSTL RX[7] RX[8] RX[9] GND_SSTL
CB6 0.1 F
TXCAP0 VCC_TXA EWRAP VCC
CPLLT 0.1 F
17
18 19
20 21 22
23 24 25
26 27
28
VCC
L1 1 H
C1* 10 F
+
CB1 0.1 F
C3* 10 F
CB2 0.1 F
CB3 0.1 F
NOTES: 1. C1*-C4* FOR LOW-FREQUENCY BYPASS. 2. VENKEL PART NUMBER C0603X7R160-104KNE, OR SIMILAR, CAN BE USED FOR 0.1 F CAPACITORS. 3. TDK P/N NL322522T-1R0J, OR SIMILAR, CAN BE USED FOR 1 H INDUCTORS.
Figure 12. Recommended power supply filtering arrangement.
20
29 30 31 32
VCC CB4 0.1 F
GND_SSTL
GND REFCLK[1]
REFCLK[0] EN_CDET
RX_LOS COM_DET
N/C RBC[1]
RBC[0]
GND
VCC
GND_TXHS VCC_TXHS SO+ SO- VCC_TXHS VCC
SI+ GND_RXA
RX_RATE VCC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 TBC TX[0] TX[1] TX[2] VREFT TX[3] TX[4] TX[5] TX[6] RBC_SYNC TX[7] TX[8] TX[9] TX_RATE GND_TXA TXCAP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 RXCAP0 VREFR GND_SSTL RX[0] RX[1] RX[2] VCC_SSTL RX[3] RX[4] RX[5] RX[6] VCC_SSTL RX[7] RX[8] RX[9] GND_SSTL
VCC_RXA RXCAP1 42 41 40 39 38 37 36 35 34 33 RBC[0] GND_SSTL
EQAMP
GND VCC
HDMP-2634 xxxx-x Rz.zz S YYWW
TXCAP0 VCC_TXA EWRAP VCC GND REFCLK[1]
REFCLK[0] EN_CDET
RX_LOS COM_DET
SI- VCC
xxxx-x = WAFER LOT NUMBER-BUILD NUMBER Rz.zz = DIE REVISION S = SUPPLIER CODE YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK) COUNTRY = COUNTRY OF MANUFACTURE (MARKED ON BACK OF DEVICE)
Figure 13. HDMP-2634 package layout and marking, top view.
21
N/C RBC[1]
GND
Package Information Item Package Material Lead Finish Material Lead Finish Thickness Lead Skew Lead Coplanarity (Seating Plane Method) Details Metric Metal QFP 85% Tin, 15% Lead 200-800 micro-inches 0.20 mm max. 0.08 mm max.
Mechanical Dimensions of HDMP-2634
PIN #1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 48 47 46 45 44 43 42 41 40
TOP VIEW
E1
E
10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
c
b D1 D e L
0.25 GAUGE PLANE
A2
A
A1 DIMENSIONAL PARAMETER (MILLIMETERS) VALUE TOLERANCE
SEATING PLANE
A 2.35 MAX.
A1 0.25
A2 2.00
D/E 17.20
D1/E1 13.80
L 0.88
b 0.37
c 0.20
e 0.80
MAX. 0.10 0.25 0.05 0.15 + 0.08/ MAX. BASIC - 0.03
22
www.semiconductor.agilent.com Data subject to change. Copyright (c) 2000 Agilent Technologies, Inc. December 14, 2000 5980-2107E

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